At a time when most of the smartphone chipsets are made using 7nm node, Unisoc recently launched the world’s first 6nm chipset which was manufactured by TSMC using extreme ultraviolet lithography (EUVL). However, other companies are not much behind.
Samsung, the world’s second largest chipset maker after TSMC, has already started mass production of 6nm and 7nm EUV (Extreme Ultraviolet) chipsets. Now, the company has announced that it plans to start mass production of 5nm chipsets.
The company has also added that it will continue to invest in advanced processes as well as GAA 3nm process. The Samsung V1 facility located in Hwaseong, South Korea, is the one where the production will take place. It is a specialised facility with state-of-the-art technology and is capable of production of chipsets as small as 3nm.
There are reports claiming that Google has partnered with Samsung for a custom Exynos chipset which is scheduled to release this year. The 5nm chipset is expected to feature an octa-core CPU consisting of two Cortex-A78 cores, two Cortex-A76 cores, and four Cortex-A55 cores. The graphics will be taken care of by an unannounced Mali MP20 GPU based on Borr microarchitecture. It is also said to include Google’s own Visual Core ISP and NPU instead of Samsung’s.
A couple of months ago, it was reported that Samsung Electronics’ semiconductor manufacturing division won a contract to make new Qualcomm 5G chips using . This is a major boost for the company to aims to rival TSMC.
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To get a lead among its competitors, Samsung was set to start mass production of 3nm chipset from 2021 but it seems that the company is now forced to delay the manufacturing launch of this new process till 2022, mainly because of the COVID-19 outbreak.
It is reported that the coronavirus has hampered Samsung’s ability to fulfil the scheduled installation of equipment for the new production lines. The 3nm process from Samsung is based on the Gate All Around (GAAFET) technology rather than FinFET. It supposedly reduces the total silicon size by 35 percent while using about 50 percent less power.
It also allows for the same amount of power consumption and 33 percent performance increase over the 5nm FinFET process. The GAAFET design differs from the FinFET design as it is built around having gates around four sides of the channel, which ensures reduced power leakage and improved control over the channel.
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