Global tech brand Samsung has announced the commencement of production of 3-nanometer (nm) chips. The process uses the Gate-All-Around (GAA) transistor architecture and yields power-efficient and performance-enhanced chips. Samsung is also developing a second-generation 3nm process node that would offer significant improvements across several areas.
Samsung says the 3nm process uses 45% less power, improves performance by 23%, and uses 16% less surface area than a 5nn process. The process node incorporates a GAA transistor architecture with larger channels in gates for electricity to flow through at a lower voltage level. This is due to the utilization of all four sides of the channels, unlike the FinFET architecture.
The adaptability of the 3nm process node means that the channel width can be modified to meet specific client demands. This milestone development of 3nm chips gives Samsung a boost in the market. Samsung is the world’s second-biggest foundry. It is, however, the chipmaker of choice and has the largest contract base globally. The largest foundry, TSMC is preparing to commence mass production using its own 3nm process node.
The Samsung Advanced Foundry Ecosystem (SAFE) partners have played a major role in helping Samsung achieve the 3nm chips milestone. These include Ansys, Cadence, Siemens, and Synopsys. Samsung will in the future broaden the applicability of the 3nm process node to mobile CPUs. Samsung is silent on the identity of the OEM that the 3nn chips are being manufactured. The first mobile devices using the 3nm chips are expected in 2023.
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