A new report from Nikkei says Chinese chipmaker SMIC is developing 3nm fabrication processes despite key equipment difficulties occasioned by US sanctions. The chipmaker has been prevented from accessing advanced chip production equipment from US vend

SMIC

SMIC is reported to have developed its 2nd-gen 7nm-class process technology that can be used to produce smartphone processors. The new report states that SMIC is pursuing research on 5nm and 3nm-class process technologies. The research is being carried out in-house by the company’s research and development team. The team is led by co-CEO Liang Mong-Song, a renowned semiconductor scientist. The team leader has had stints at TSMC and Samsung. He is rated as one of the most brilliant minds in the semiconductor industry.

The news is quite instructive that the US sanctions regime has not been able to completely halt the progress of SMC in developing advanced chips beyond the 7nm process. It may have seriously slowed down the company, but a combination of factors is working in its favor in overcoming the challenges.

SMIC is currently the fifth-largest contract maker of chips in the industry. It lost access to leading-edge wafer fab tools that severely limited its ability to adopt new process technologies. As a result of the sanctions, SMIC was unable to get extreme ultraviolet (EUV) lithography tools from ASML. It however relied solely on deep ultraviolet (DUV) lithography for its 2nd-gen 7nm-class node.

The ASML Twinscan NXT:2000i lithography machines are the best tools available to SMIC currently. They can etch up to 38nm production resolutions. The level of precision is adequate for printing 38nm metal pitches using double patterning for 7nm-class nodes. Metal pitches shrink to 30-32nm at 5nm and 21-24nm at 3nm, according to AML and IMEC.

Multi-patterning is another option for achieving ultra-small feature sizes that can omit the use of EUV. It is a complicated process that lengthens the cycle times and can affect yields, as well as wear down the fabrication equipment. The cost implications for multi-patterning is also quite high. SMIC is using triple, quadruple, or sometimes, quintuple patterning to achieve lower resolutions. The design of a DUV-only 3nm-class fabrication process is a significant milestone for SMIC. It remains to be seen how the chip will perform in products.

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